The present invention relates to reconfigurable semiconductor storage devices.
Traditionally, integrated circuit (IC) devices such as custom, semi-custom, or application specific integrated circuit (ASIC) devices have been used in electronic products to reduce cost, enhance performance or meet space constraints. However, the design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. In the event of finding a logic error in the custom or semi-custom IC during final test phase, the design and fabrication cycle has to be repeated. Such lengthy correction cycles further aggravate the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost applications.
Another type of semi custom device called a Gate Array customizes modular blocks at a reduced NRE cost by synthesizing the design using a software model similar to the ASIC. The missing silicon level design verification results in multiple spins and lengthy design iterations.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. The flexibility of this programmability is expensive in terms of silicon real estate, but reduces design cycle and upfront NRE cost to the designer.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches. Compared to PLD and FPGA, an ASIC has hard-wired logic connections, identified during the chip design phase. ASIC has no multiple logic choices and no configuration memory to customize logic. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count PLD or FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost and better reliability (ASIC advantage). The cost of Silicon real estate for programmability provided by the PLD and FPGA compared to ASIC determines the extra cost the user has to bear for customer re-configurability of logic functions.
Multi-input and multi-output digital logic systems are classified into combinational and sequential logic. Combinational logic has no memory and the outputs reflect a function solely of present inputs. Sequential logic is implemented by inserting memory into the logic path. This allows present input states as well as past input and past output states to determine the present output. In sequential logic the logic output and logic inputs can be stored and re-used as inputs at a later time point. Many such logic systems include clocks, preset and clear signals and are classified into synchronous and asynchronous systems. A storage element is used to store information about the previous condition of the sequential logic system. The most common bistable circuit in use is a multivibrator, or commonly called flip-flop. In a sequential circuit, these flip-flops can be by passed to facilitate combinational logic. Flip-flops contain two inverting gates cross-coupled in a positive feed back to assume one of two stable output states. There are many types of flip-flops available for use: SR, JK, Clocked JK, T, D with and without Preset and Clear options. They provide a pair of complementary outputs and contain one or more inputs that can cause the output state to change. FIG. 1 shows a schematic diagram of three basic flip-plops: SR in FIG. 1A, JK in FIG. 1B and D in FIG. 1C. The complementary outputs are customarily labeled Q and Q′ (not Q). The inputs are labeled S, R, J, K or D in each of the respective flip-flops. The user application determines the best option for the flip-flop in the logic design.
A flip-flop has a present state and a next state. The present state means the state of Q output in FIG. 1 at the time input signals are applied or changed. The next state means the state of Q output after the flip-flop has reacted to the inputs signals. The transient time taken for the flip-flop to stabilize is carefully avoided in the logic design. Each flip-flop has a well defined sequence for its output behavior in response to input signals. This next state sequence differs from one flip-flop to another and can be characterized by a Characteristic Equation, State Graph, Truth Table, and Karnaugh Map. Examples of characteristic equations and truth tables for some of the flip-flops in FIG. 1 are shown in FIG. 2. As shown in FIG. 2, the undesired states in SR flip-flop are removed in the JK flip-flop, while the D flip-flop has only a single input and an output reflecting that input.
A master-slave flip-flop is a structure where input and output terminals are kept disjoint. A common arrangement is to cascade two flip-flops and clock data in complementary signals. The master flip-flop captures data from inputs on one phase of the clock, while the slave flip-flop captures data from the master flip-flop in the opposite phase of the clock.
Existing PLD and FPGA architectures utilizing flip-flops are discussed in Hartmann U.S. Pat. No. 4,609,986, Carter U.S. Pat. No. 4,706,216, Turner et al. U.S. Pat. No. 4,761,768, Norman et al. U.S. Pat. No. 4,864,161, Freemann U.S. Pat. No. 4,870,302, ElGamal et al. U.S. Pat. No. 4,873,459, Freemann et al. U.S. Pat. Nos. 5,488,316 & 5,343,406, Trimberger et al. U.S. Pat. No. 5,844,422, Cliff et al. U.S. Pat. No. 6,134,173, Couts-Martin et al. U.S. Pat. No. 6,097,211, Mendel U.S. Pat. No. 6,275,065 and Young et al. U.S. Pat. No. 6,448,808. These have flip-flops embedded in basic the logic elements of an FPGA fabric or the macro-cells of a PLD fabric. FPGA's and PLD's are constructed with a repetitive pattern consisting of these basic building blocks. A routing block is programmed to define inputs and outputs to the logic blocks, while the logic block performs a specific logic function. Such a logic block described in Ref-1 is shown in FIG. 3, which has a built in fixed D-flip-flop. In FIG. 3, elements 301, 302 and 303 are 2:1 MUX's controlled by one input signal. Element 304 is an OR gate while 305 is a D-Flip-Flop. Eight inputs feed the logic block. All two-input, most 3-input and some 4-input variable functions are realized in the logic block and latched to the D-Flip-Flop. The Flip-Flop in itself offers no configurable capability. Most FPGA's and PLD's referenced earlier have a similar built-in D Flip-Flop inside the logic block. An AND, NOR gate realization of a clocked D-Flip-Flop with Preset and Clear functions is shown in FIG. 4. In FIG. 4, element 401 is an inverter, 402 and 403 are 2-input AND gates and 404 and 405 are 3-input NOR gates. This can be customized by the user only with the logic content available in that and neighboring logic elements. Overall logic capacity is thus reduced from configuring flip-flops outside of what is provided by the manufacturer and the available logic density for the application is drastically reduced.
Kaplinsky U.S. Pat. No. 5,164,612, Orgill et al. U.S. Pat. No. 5,684,744, Kelem U.S. Pat. No. 6,061,417 and Fifield et al. U.S. Pat. No. 6,420,925 have discussed programmability with respect to latches, registers and flip-flops. These implementations are either very high in Silicon area, or provide little flexibility for user change. A useful measure of a programmable circuit is the gate comparison to an equivalent specific application circuit. In most programmable devices, after the user has finalized the logic design, it is rarely or never changed. For these designs, a conversion from programmable to application specific is highly desirable. The referenced usages do not lend to an easy economical conversion. An inexpensive, single configurable storage device that will allow the user the flexibility in picking the most desired flip-flop type from a variety of choices is highly desirable for programmable logic applications. Such a design should also lend to an easy application specific design conversion to the user, preserving the original timing characteristics of the circuit during the conversion.